1. Field of the Invention
This invention relates to circuitry for checking the synchronization of clocks employed in data processing and transmission systems and, more particularly, to checking synchronization through the utilization of appropriately delayed signals.
2. Description of the Prior Art
In complex systems for data processing and transmission, e.g.--telephone networks and computer systems, several synchronized clocks are frequently used. They either control various sub-systems, being at a considerable distance from each other, or they act as a reserve for taking over control of the system should there be a failure of the main clock. In either of these cases, it is critically necessary to insure that these clocks are in synchronization at any moment. For that purpose, check circuits are required to verify that the clock signals have not gradually shifted with respect to each other, whether there is a failure of one of the clocks, whether individual clock pulses are missing or whether there is an overall clock failure.
As a means of monitoring the individual clocks, the prior art has made use of simple logic circuits, such as AND gates, to which corresponding pulses of the various clocks are applied. One example of this type of clock monitoring means is shown by U.S. Pat. No. 3,600,690 to White.
In other cases, e.g.--in German Offenlegungssehrift No. 25 32 587, counters associated with the various clocks and comprising comparators are used to emit an error signal upon sensing an unequal count indicative of clock malfunction. German Auslegischrift No. 15 13 062 describes an arrangement wherein a multivibrator is impressed with the setting or resetting signals of two clocks. Upon the failure of a clock, the multivibrator stops and an associated capacitor is discharged to release an alarm signal.
However, these known clock checking arrangements are not suited for data processing and transmission systems, particularly modern computers having several synchronized clocks utilized therein. These clocks are part of the control circuitry of the computer, which is a complicated arrangement and therefore very difficult to examine for error conditions. It is necessary in connection with the malfunction checking of such circuitry that all errors appearing in the clocks themselves be fully detected and distinguished from other possible errors in the control circuitry. For that purpose, not only must the clock synchronism existing at any moment be checked, but also the dynamic behavior of the various clocks, i.e.--the relative position of time signals within a specific interval, needs to be verified.
Unfortunately, this cannot be done by simple logic gates. Furthermore, the checking device has to be able to detect the simultaneous stoppage of several clocks. This is not possible, either, through the use of simple logic gates and counters. In addition, the error indication has to take place immediately after the appearance of an error. Finally, another obvious demand is that the checking circuitry be easily realizable as a highly integrated circuit.